1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a level adjustment circuit including a circuit operated by an inside power source voltage (VDD) and a data output circuit thereof.
2. Description of Related Art
A level adjustment circuit for converting logic amplitude from an inside power source voltage (VDD) level to an outside power source voltage (VCC) level includes two NMOS transistors and two PMOS transistors connected to VCC and ground power source voltage. Each source electrode of the PMOS transistors is connected to VCC. Further, a gate electrode and a drain electrode are connected in a cross-coupling way with each other, and each of them is connected to the output node. An output level of this type of conventional level adjustment circuit is determined by the ON resistance ratio of the PMOS transistor and the NMOS transistor.
However, according to the conventional circuit, there is a problem in which a time interval is long between time at which a logic level of data and the output control signal changes, and time at which a logic level of an output and level adjustment circuit changes, thus it is desired to improve the speed.
The object of the present invention is to provide a level adjustment circuit to shorten the time interval between the time at which a logic level of an output control signal of data changes and the time at which the logic level of an output of the level adjustment circuit changes. A level adjustment circuit of the present invention includes a MOS transistor for pulling up an output node, a first inverter for inputting output data signal and outputting a gate control signal for controlling a gate electrode of the MOS transistor, and a second inverter connected to the MOS transistor in series between first and second power sources for inputting a first node obtained based on the output data signal, and outputting the output node. The data output circuit of the present invention includes a first inverter connected to the first and second power sources for inputting output data signal and outputting to a first node, and a level adjustment circuit connected to the second power source and a third power source, electric potential of which is higher than the first power source, for outputting to a second node, in which the level adjustment circuit has a first MOS transistor for pulling up the second node, and a second inverter connected to the first MOS transistor in series between the second and third power sources; and a third inverter for inputting the data signal and outputting a gate control signal for controlling a gate electrode of the first MOS transistor.